Piezoelectric device and method for manufacture thereof

ABSTRACT

An opening is formed in the center of a base on which an input/output electrode pattern is formed. Meanwhile, a plurality of bumps are formed on two opposing sides of an active element surface of the semiconductor integrated circuit so as to mount the semiconductor integrated circuit in the center of the opening. The semiconductor integrated circuit is connected to the electrode pattern on the base through the plurality of bumps by ultrasonic bonding. In this way, a small and thin piezoelectric device which has superior bonding characteristics of the semiconductor integrated circuit and the base, which are subjected to flip-chip bonding, and which endures mechanical shock, thermal stress, etc., can be obtained at reduced cost.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a piezoelectric device in which asemiconductor integrated circuit and a piezoelectric resonator elementare included in a package, and to a method for manufacturing the same.

2. Description of Related Art

In recent years, hard disk drives (HDD), mobile computers, informationapparatuses such as IC cards and portable communication apparatuses suchas cellular phones, phones for automobiles have undergone dramaticminiaturization. Accordingly, piezoelectric devices such aspiezoelectric oscillators, voltage-controlled oscillators (VCXO),temperature-compensated oscillators (TCXO), SAW oscillators, real timeclock modules for use in these apparatuses are also required to besmaller and thinner. Also, surface-mounting type piezoelectric devicescapable of being mounted on both sides of the circuit board of thedevice are desired.

An example of a conventional piezoelectric device will be explainedusing a quartz crystal oscillator shown in structural diagrams of FIGS.16(A) and 16(B), the quartz crystal oscillator using a semiconductorintegrated circuit of single-chip type having an oscillating circuit andan AT-cut quartz crystal resonator as a piezoelectric resonator element.

In the conventional quartz crystal oscillator in FIGS. 16(A) and 16(B),an IC chip 101 having an oscillating circuit is bonded and fixed by aconductive adhesive, etc., to the bottom face of a base 102 formed of aceramic insulating substrate, is electrically connected by Auwire-bonding lines 103 to input/output electrodes 104 at the externalperiphery of the bottom face of the base 102. The input/outputelectrodes 104 are metallized by metal such as tungsten (W), molybdenum(Mo) and are plated in multiple layers by Ni plating and Au plating,etc. More specifically, a plurality of electrodes 108 are provided inthe IC chip 101 and the electrodes 108 are electrically connected to theabove-described input/output electrodes 104, etc., by the wire-bondinglines 103.

A rectangular-shaped AT-cut quartz crystal resonator 105 is electricallyconnected to a mounting portion 106 of the base 102 and is fixed theretoby a conductive adhesive or the like. A plated layer at the top portionof the base 102 and a metallic lid 107 are connected by melting ametallic cladding material such as solder formed on the lid 107 at ahigh temperature so as to provide a hermetic seal, while maintaining anN₂ (nitrogen) atmosphere or to a vacuum atmosphere in the inner portion.

SUMMARY OF THE INVENTION

The above-described conventional quartz crystal oscillator requires anarea around the IC chip 101 for wiring the Au wire-bonding lines 103,and a sufficient height in the direction of the package thickness mustbe secured to accommodate the loops of the Au wire-bonding lines 103.Also, a gap must be provided between the Au wire-bonding lines 103 andthe AT-cut quartz crystal resonator 105. Such a configuration preventsfurther miniaturization of quartz crystal oscillators.

Objects of the present invention are to solve the above-describedproblems and to provide at reduced cost a small and thin piezoelectricdevice, such as a quartz crystal oscillator, which can withstandmechanical impacts and has a thickness of 1 mm or less, and to provide amethod for manufacturing the piezoelectric device.

One exemplary embodiment of the present invention is a piezoelectricdevice including a semiconductor integrated circuit and a piezoelectricresonator element both included in a package, wherein an opening isformed in the center of a base provided with an input/output electrodepattern, the semiconductor integrated circuit is mounted in the centerof the opening, and the semiconductor integrated circuit is connected tothe electrode pattern on the base through a plurality of bumps.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the plurality of bumps formed onthe semiconductor integrated circuit are formed at regular intervals onthe center portion of an active element surface of the semiconductorintegrated circuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the plurality of bumps formed onthe semiconductor integrated circuit are concentrically formed about thecenter of an active element surface of the semiconductor integratedcircuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, a dummy bump is formed on theactive element surface of the semiconductor integrated circuit.

In another exemplary embodiment of the present invention in thepiezoelectric device described above, the dummy bump formed on thesemiconductor integrated circuit is connected to the electrode patternon the base.

In another exemplary embodiment of the present invention, thepiezoelectric device described above further includes a layered part,which surrounds the semiconductor integrated circuit, for mounting thepiezoelectric resonator, the layered part including at least two layers,including a first layer and a second layer, wherein an opening of thefirst layer is formed to be larger than an opening of the second layer.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, each of the plurality of bumpsformed on the semiconductor integrated circuit is shaped to have twolevels, one having a diameter 0.8 to 0.9 times and the other having adiameter 0.4 to 0.45 times the length of a side of an opening in a padprovided on an active element surface of the semiconductor integratedcircuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the base may consist of a ceramiccomposite substrate.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, each of the plurality of bumpsformed on the semiconductor integrated circuit is an Au bump.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, a protrusion is formed in at leastone side wall of the base facing the side of the semiconductorintegrated circuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the protrusion is formed in eachof the side walls of the base facing the two sides along thelongitudinal direction of the semiconductor integrated circuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the protrusion formed in the sidewall of the base has substantially the same height as, or is higherthan, the semiconductor integrated circuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, a gap between the protrusionformed in the side wall of the base and the semiconductor integratedcircuit is set to a range between 0.05 and 0.15 mm.

Another exemplary embodiment of the present invention is apiezoelectric, device including a semiconductor integrated circuit and apiezoelectric resonator element included in a package, wherein anopening is formed in the center of a base provided with an input/outputelectrode pattern, a plurality of bumps are formed at two opposing sidesof an active element surface of the semiconductor integrated circuit,the semiconductor integrated circuit is mounted in the opening, and thesemiconductor integrated circuit is connected to the electrode patternof the base through the plurality of bumps.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the plurality of bumps formed onthe semiconductor integrated circuit are formed at regular intervals atthe center portion of the active element surface of the semiconductorintegrated circuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, a dummy bump is formed on theactive element surface of the semiconductor integrated circuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the dummy bump formed on thesemiconductor integrated circuit is connected to the electrode patternon the base.

In another exemplary embodiment of the present invention, thepiezoelectric device described above, further includes a layered part onwhich the piezoelectric resonator is mounted and which surrounds thesemiconductor integrated circuit, the layered part including at leasttwo layers including a first layer and a second layer, wherein anopening of the first layer is formed to be larger than an opening of thesecond layer.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, each of the plurality of bumpsformed on the semiconductor integrated circuit is shaped to have twolevels, one having a diameter 0.8 to 0.9 times and the other having adiameter 0.4 to 0.45 times the length of an opening in a pad provided onthe active element surface of the semiconductor integrated circuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the base includes a ceramiccomposite substrate.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the plurality of bumps formed onthe semiconductor integrated circuit are Au bumps.

Another exemplary embodiment of the present invention is a piezoelectricdevice including a semiconductor integrated circuit and a piezoelectricresonator element included in a package, wherein an opening is formed inthe center of a base provided with an input/output electrode pattern isformed, a plurality of bumps are formed at two opposing sides of anactive element surface of the semiconductor integrated circuit, thesemiconductor integrated circuit is mounted in the center of theopening, and the semiconductor integrated circuit is connected to theelectrode pattern through the plurality of bumps by ultrasonic bonding.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, a vibration direction ofultrasonic waves applied to the semiconductor integrated circuit isperpendicular to the two opposing sides of the active element surface ofthe semiconductor integrated circuit at which the plurality of bumps areformed.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, a printing direction of theelectrode pattern on the base and a vibration direction of ultrasonicwaves applied to the semiconductor integrated circuit are the same.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, each of the plurality of bumpsformed on the semiconductor integrated circuit is shaped to have twolevels, one having a diameter 0.8 to 0.9 times and the other having adiameter 0.4 to 0.45 times the length of an opening in a pad provided onthe active element surface of the semiconductor integrated circuit.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, each of the plurality of bumpsformed on the semiconductor integrated circuit is shaped to have twolevels, one being 80 to 90 μm in diameter and 30 to 35 μm in height, andthe other being 40 to 45 μm in diameter and 30 to 35 μm in height.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the base consists of a ceramiccomposite substrate.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the plurality of bumps formed Onthe semiconductor integrated circuit are Au bumps.

In another exemplary embodiment of the present invention, in thepiezoelectric device described above, the longitudinal direction of theelectrode pattern on the base and a vibration direction of-ultrasonicwaves applied to the semiconductor integrated circuit are the same.

In another exemplary embodiment of the present invention, thepiezoelectric device described above includes the semiconductorintegrated circuit and the piezoelectric resonator element in includedin the package, wherein a vibration direction of ultrasonic waves forultrasonic bonding and for forming bumps on the semiconductor integratedcircuit and a vibration direction of ultrasonic waves for performingultrasonic bonding of the semiconductor integrated circuit to thepackage are different from each other.

Another exemplary embodiment of the present invention is a method formanufacturing a piezoelectric device including a semiconductorintegrated circuit and a piezoelectric resonator element included in apackage, the method may include: a step of forming a metallic bump onthe semiconductor integrated circuit; a step of connecting thesemiconductor integrated circuit on which the metallic bump is formed tothe base by ultrasonic bonding; a step of detecting a height directionof the semiconductor integrated circuit during the ultrasonic bonding; astep of mounting the piezoelectric resonator element; and a step ofhermetically sealing a metallic lid to the base.

Another exemplary embodiment of the present invention is a method for rmanufacturing a piezoelectric device including a semiconductorintegrated circuit and a piezoelectric resonator element included in apackage, the method may include: a step of forming a metallic bump onthe semiconductor integrated circuit; a step of connecting thesemiconductor integrated circuit on which metallic bump is formed to thebase by ultrasonic bonding; a step of detecting a height direction ofthe semiconductor integrated circuit during the ultrasonic bonding step;a step of filling an underfill material around the semiconductorintegrated circuit so as to cover the entire semiconductor integratedcircuit including a rear surface of the semiconductor integratedcircuit; a step of mounting the piezoelectric resonator element; and astep of hermetically sealing a metallic lid to the base.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(A)-(B) are structural diagrams of a piezoelectric deviceaccording to the present invention;

FIG. 2 is a diagram illustrating the formation of a bump on a wafer ofthe piezoelectric device of the present invention;

FIG. 3 is a diagram showing the shape of the bump of the piezoelectricdevice of the present invention;

FIG. 4 is a diagram showing the shape of another bump of thepiezoelectric device of the present invention;

FIG. 5 is a process diagram illustrating a flip-chip bonding process ofthe present invention;

FIG. 6 is a stress distribution map according to FEM analysis;

FIG. 7 is a structural diagram showing another embodiment of the presentinvention;

FIG. 8 is a structural diagram showing another embodiment of the presentinvention;

FIG. 9 is a structural diagram showing another embodiment of the presentinvention;

FIGS. 10(A)-(B) are a plan view and a front view, respectively, showinganother embodiment of the present invention;

FIGS. 11(A)-(B) are a plan view and a front view, respectively, showinganother embodiment of the present invention;

FIG. 12 is a structural diagram showing another embodiment of thepresent invention;

FIG. 13 is a structural diagram showing a cross-section of a bondedportion of the present invention;

FIG. 14 is a structural diagram showing yet another embodiment of thequartz crystal oscillator of the present invention;

FIG. 15 is an enlarged plan view showing a structure of a portion AR inFIG. 14; and

FIGS. 16(A)-(B) are structural diagrams of a conventional piezoelectricdevice.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The preferred embodiments of the present inventions will be describedbelow with reference to the drawings.

An embodiment of a piezoelectric device of the present invention isdescribed with reference to the drawings, using as an example a quartzcrystal oscillator having a single-chip-type semiconductor integratedcircuit having an oscillation circuit and an AT-cut quartz crystalresonator element as a piezoelectric resonator element.

Embodiment 1

FIGS. 1(A)-(B) are structural diagrams of a surface-mount type quartzcrystal oscillator according to an embodiment of the present invention.

As shown in a plan view of FIG. 1(A) and in a front view of FIG. 1(B),on a first layer of a base 1 consisting of a ceramic insulatingsubstrate having at least three layers and a seal ring of Fe—Ni alloy orthe like, stamped to a frame shape, an electrode pattern 3 for forming aconnection with a semiconductor integrated circuit (IC chip: hereinafterreferred to as the IC chip) 2 is metallized by means of printing byusing metal wiring material such as W (tungsten), Mo (molybdenum). Onthe top thereof, Ni plating and Au plating, etc., are provided.

On an electrode pad of the IC chip 2, a metallic bump 4 made of Au orthe like is formed and, by a flip-chip bonding method, is connected tothe electrode pattern 3 formed on the base 1. Among various techniquesof the flip-chip bonding method, the method employed in the presentembodiment is one using ultrasonic waves to yield an Au—Au solid statebond.

A supported portion 7 of an AT-cut quartz crystal resonator 6 isconnected and fixed by a conductive adhesive 9 to a mounting portion 8provided in a second layer 5 of the base 1.

A metallic lid 11 is aligned with a seal ring 12 formed of an Fe—Nialloy or the like die-cut into a frame shape, is fixed, and ishermetically sealed by seam welding.

Accordingly, a small and thin surface-mounted package type quartzcrystal oscillator 13 is obtained.

Next, a bump forming process for forming the bump 4 made of Au or thelike on the IC chip 2, and a flip-chip bonding process for connectingthe IC chip Z to the electrode pattern 3 formed on the base 1 will bedescribed in detail.

For example, as shown in FIG. 2, on pads 14 of the wafer IC chip 2 whichis 4 to 6 inches, a plurality of bumps 4 are formed by ultrasonic bumpbonding using fine Au bonding lines each having a diameter of, forexample, approximately 25 to 35 μm.

There are several possible shapes for the bump 4; in this embodiment, asshown in FIG. 3, the bump 4 having two levels is formed.

When a side of a pad opening 15 of the pad 14 of the IC chip 2 has alength A, the bump 4 is shaped to have two levels, one having a diameterof 0.8A to 0.9A, another having a diameter of 0.4A to 0.45A.

Described in terms of specific figures, when the length of one side ofthe pad opening 15 in the typical pad 14 is 100 μm, the bump 4preferably has two levels, one being 80 to 90 μm in diameter and 30 to35 μm in height, the other being 40 to 45 μm in diameter and 30 to 35 μmin height.

In order to form bumps on a number of (approximately several thousand)wafer IC chips 2, the working temperature for forming the bumps ispreferably low and, in this embodiment, the bumps are worked at atemperature of approximately 180° C. The experiments and evaluationsregarding jointing strength and range of eutectic show that thepreferable temperature is, for example, a temperature in a range of 180°C. to 230° C.

In order to improve the flatness of the tip portion of the second stageof the bump 4, the tip portion of the bump 4 may be crushed and leveledas shown in FIG. 4.

Next, a flip-chip bonding process for bonding the IC chip 2 providedwith the bumps 4 of the above-described shape to the base 1 will bedescribed in detail.

FIG. 5 is a process diagram illustrating a flip-chip bonding process.

The wafer IC chip 2 is picked up by a nozzle such as an invertedpyramidal collet, is turned over, and is passed on to an nozzle tip ofan ultrasonic horn. Then, the IC chip 2 is aligned and is chip-mountedon a mounting area of the base 1 with high precision by a system such asan image recognition system provided in the flip-chip bonding apparatus.

When the IC chip 2 contacts the electrode pattern 3 of the base 1 andload is detected by the flip-chip bonding apparatus, weight is appliedat 100 grams per bump and, ultrasonic waves are simultaneously appliedto bond Au in the bump 4 and Au in the electrode pattern 3 in a solidstate. The conditions of the ultrasonic waves are determined by thepower of ultrasonic waves and application period of the ultrasonicwaves. In order to conduct the bonding, a proper temperature isrequired, and the base 1 is preheated at, for example, a temperature ina range between approximately 150° C. and 200° C. The base 1 is alsoheated in a similar manner during the ultrasonic wave processing.

In the flip-chip bonding apparatus, a sensor for detecting a heightdirection of the IC chip 2 is provided and by checking and controllingthe height data, the process can be carried out as if the height of thebumps 4 were uniform.

The working parameters employed in the present embodiment is to applyload of approximately 100 grams per bump and, for the parameters of theultrasonic waves, a parameter value determined by the size of the ICchip 2 and the number of the bumps 4 is used.

FIG. 6 is a stress distribution map of the IC chip 2 and the vicinity ofthe bumps 4 during reflow using FEM (Finite Element Method) analysis orwhen thermal stress due to a cycling test, etc., is applied to thequartz crystal oscillator 13.

From this stress distribution map, it can be understood that the stressvalue is varied depending on the position of the bump and thatsignificant stress concentration acts in the vicinities of the bumps 4arranged at the corners of the IC chip 2 and in the portion with fewerbumps 4.

When the stress is applied to the vicinity of the bumps 4 as describedabove, a failure such as the bump 4 and the electrode pattern 3 becomingdisconnected, is likely to occur. Such failure is likely to occurespecially when a high temperature such as that during reflow issuddenly applied to the quartz crystal oscillator 13. Such failure mayalso occur due to aging, dropping a device such as a portable devicehaving the thin quartz crystal oscillator 13 inside, and mechanicalshock such as vibrations.

The thermal stress and mechanical stress due to dropping and vibrationare related to the overall structure of the base 1, and it is anotherobject of the present invention to provide a configuration of the quartzcrystal oscillator 13 in which stress is not concentrated around thebump 4. Essential points of such a configuration will be describedbelow.

As shown in FIGS. 1(A)-(B), a configuration in which an opening 16 isformed in the center of the base 1 and the IC chip 2 is mounted in thecenter of the opening 16 is employed. Thus, when the quartz crystaloscillator 13 is exposed to stress, by this configuration, the stress isevenly applied to the IC chip 2, preventing the stress fromconcentrating in a specific portion.

Next, a configuration in which dummy bumps 17 are formed will beexplained. The dummy bumps 17 are connected to an electrode pattern 18laid out on the base 1. In this embodiment, the electrode pattern 18 isnot connected to the input/output electrodes and is configured to beelectrically isolated.

By employing the structure with the dummy bumps 17 formed, the arrays ofthe bumps 4 at two opposing sides become even, equally sharing thestress applied to the vicinity of the bumps 4.

Consequently, in this configuration, stress is not concentrated in aspecific area and well-balanced bonding characteristics resistant tothermal stress and mechanical stress can be obtained.

Next, the direction in which ultrasonic waves are applied anddeformation of the bumps 4 will be described.

During the process of applying ultrasonic waves to perform solid statebonding of Au in the bump 4 and Au in the electrode pattern 3, theinitial two-level shape of the bump 4 shown in FIG. 3 is deformed andconnected. At this time, in order to prevent a short-circuit between theadjacent bumps 4 and in order to perform bonding of all the bumps 4 andthe electrode pattern 3 in an even manner, the way in which the bumps 4are arrayed relative to the application direction of the ultrasonicwaves, the directions in which the electrode pattern 3 is printed on thebase 1, and the direction in which the ultrasonic waves are applied areregulated.

To be specific, the bonding process is carried out in such a manner thatthe vibration direction of ultrasonic waves applied to the IC chip 2 issubstantially perpendicular to the two opposing sides of an activeelement surface of the IC chip 2 provided with the plurality of thebumps 4.

FIG. 13 is a sectional view showing the bonded portion of the electrodepattern 3 and the bump 4.

Because the electrode pattern 3 is formed by applying electrode materialby thick-film printing, both ends thereof sag, and the bump 4 and theelectrode pattern 3 are not bonded at such portions.

Accordingly, when the process is performed by-adjusting the vibrationdirection of the ultrasonic waves to be perpendicular to thelongitudinal direction of the electrode pattern 3, there is a problem inthat bonding is not carried out in an even manner and that sufficientjointing force cannot be obtained. Thus, in this embodiment, the bondingprocess is carried out in such a manner that the vibration direction ofthe ultrasonic waves applied to the IC chip 2 is set to be the same asthe longitudinal direction of the electrode pattern 3 on the base 1 andthe printing direction of the electrode pattern 3.

Next, a process for mounting the AT-cut quartz crystal resonator 6 tothe base 1 will be explained.

As shown in FIGS. 1(A)-(B), the AT-cut quartz crystal resonator 6 isconnected and fixed by the conductive adhesive 9 to mounting electrodes21 and 22 of the mounting portion 8 provided in the second layer 5 ofthe base 1.

Then, the entire package including the IC chip 2 and the AT-cut quartzcrystal resonator 6 are subjected to an annealing treatment at a hightemperature while hardening the conductive adhesive 9. This also has theeffect of removing gasses emitted from the conductive adhesive 9, thebase 1, and so forth. Generally, the treatment is carried out for 1 to 2hours at a high temperature in a range between 200° C. and 300° C.

By this thermal treatment, an Al—Au eutectic reaction in the bump 4, anAu—Au solid-state bonding reaction, stress release in the bondedportion, and so forth are promoted, and bonding characteristics such asbonding strength of the bump 4 change. In this embodiment, conditionsfor forming the bump 4 and conditions for the flip chip bonding aredetermined taking into consideration such heat history after the flipchip bonding.

Furthermore, the metallic lid 11 is aligned with the seal ring 12 ofFe—Ni alloy or the like, which is stamped into a frame shape, on thebase 1, and is hermetically sealed by seam welding.

Embodiment 2

FIG. 7 is a plan view illustrating the structure of a quartz crystaloscillator of another embodiment of the present invention.

This quartz crystal oscillator has a structure in which a plurality ofbumps 4 are formed at regular intervals on the center portion of theactive element surface of the IC chip 2.

By employing this structure, the stress applied to the bumps 4 can beevenly distributed and a disconnection failure of the bump 4 and theelectrode pattern 3 is eliminated. Also by employing this structure, thebonding process using ultrasonic waves is carried out in a well-balancedmanner, and failure such as the IC chip 2 being mounted in a slantedmanner is eliminated.

Embodiment 3

FIG. 8 is a plan view illustrating the structure of a quartz crystaloscillator according to yet another embodiment of the present invention.

This quartz crystal oscillator has a structure in which a plurality ofbumps 4 formed on the IC chip 2 are concentrically formed about thecenter of the active element surface of the IC chip 2.

As in Embodiment 2, the stress applied to the bumps 4 can be evenlydistributed, and a disconnection failure of the bump 4 and the electrodepattern 3 is eliminated. Also, the bonding process using ultrasonicwaves is carried out in a well-balanced manner, and failure such as theIC chip 2 being mounted in a slanted manner is eliminated.

Embodiment 4

FIG. 9 is a structural diagram showing the structure of a quartz crystaloscillator according to still another embodiment of the presentinvention.

In this quartz crystal oscillator, an underfill material 23 is appliedso as to cover the rear surface of the IC chip 2. This underfillmaterial 23 not only enhances the reliability of the bonding, but alsoserves to radiate heat from the IC chip 2 by improving thermalconductivity.

Furthermore, in order for theunderfill material 23 to property permeateto the bonded portion of the bumps 4, the second layer 5 on which theAT-cut quartz crystal resonator 6 is mounted may include two layers,i.e., a first layer 24 and a second layer 25. The opening portion of thefirst layer 24 is formed to be larger than the opening portion of thesecond layer 25. By forming the second layer 25 in such a manner, theunderfill material 23 properly permeates to the bonded portion of thebumps 4 and a highly reliable bonding structure is obtained.

FIGS. 10(A) and 10(B) are structural diagrams showing the structure of aquartz crystal oscillator according to yet another embodiment of thepresent invention.

As shown in FIG. 10(A), in this quartz crystal oscillator, for example,protrusions 31 are formed in the side walls of the base 1 which face thetwo sides along the longitudinal direction of the IC chip 2. A gap 32between the IC chip 2 and the protrusion 31 is set to be 0.05 to 0.15mm, for example. In this embodiment, the gap 32 is set to 0.15 mm, forexample.

As in Embodiment 1, on the electrode pad of the IC chip 2, the bump 4made of metal such as Au is formed and is connected by the flip-chipbonding process to the electrode pattern 3 formed on the base 1.

Next, the method for applying the underfill material 23 on the rearsurface of the IC chip 2 so that the underfill material 23 completelyfills, without gap, the portion of the IC chip 2 in which the bumps 4are provided, as shown in FIGS. 11(A) and 11(B), will be explained indetail.

The underfill material 23 applied to the IC chip 2 through an applicatorsuch as a dispenser, only spreads over the rear surface of the IC chip 2due to surface tension, as shown in FIG. 11(B), and is prevented fromflowing to the region with the bumps 4.

Then, as shown in FIG. 11(A), the protrusions 31 are formed on the sidewalls of the base 1 facing the two sides along the longitudinaldirection of the IC chip 2. Because of these, the underfill material 23applied through the applicator such as the dispenser contacts theprotrusions 31 at the peripheral portion thereof, and spreads. Theunderfill material 23 permeates the gap 32 between the IC chip 2 and theprotrusions 31, and completely fills the portion of the IC chip 2provided with the bumps 4, without gaps.

Here, a width L of the protrusions 31 is set to ⅓ to ½ of the width L0of the IC chip 2. By so setting the dimension of the width of theprotrusion 31, the underfill material 23 is prevented from overflowingthe mounting portion 8, etc. It also serves to urge the underfillmaterial 23 to spread to the region of the IC chip 2 provided with thebump 4.

As shown in FIG. 10(B), the protrusions 31 are formed to be higher thanthe rear surface R of the IC chip 2 and are formed down to the bondingsurface S of the base 1 to which the bumps 4 are connected. By thusforming the protrusions 31, the underfill material 23 is prevented fromspreading upward along the side wall of the base 1 and from spreadingtoward the mounting portion 8 of the AT-cut quartz crystal resonator 6.Formation of the protrusions 31 also serves to urge the underfillmaterial 23 to spread to the bonding surface of the base 1.

The gap 32 only needs to be wider than the particles of the underfillmaterial 23, and, ideally, 0.05 mm is optimum from various permeationcharacteristic experiments concerning the underfill material 23.

The protrusion 31 may be shaped to have recesses 33, as shown in FIG.12.

Consequently, as shown in FIG. 10(B), the underfill material 23completely fills the gap provided at the portion of the IC chip 2 havingthe bumps 4, and covers the vicinity of the bumps 4.

The underfill material 23 not only enhances the reliability of thebonding, but also serves to radiate the heat from the IC chip 2 byimproving thermal conductivity.

As in the above, by using highly reliable and inexpensive componentssuch as ceramic and metal, a thin and small, for example, 2 to 3.2 mm inlength, 2 to 2.5 mm in width, and 0.7 to 1.0 mm in thickness,piezoelectric oscillator of high reliability can be provided at reducedcost.

Embodiment 6

FIG. 14 is a structural diagram illustrating the structure of a quartzcrystal oscillator according to yet another embodiment of the presentinvention; and FIG. 15 is an enlarged plan view showing a structure of aportion AR in FIG. 14.

During the process for forming the bumps, as shown in FIG. 2, theplurality of bumps 4 are formed on the pads 14 of the wafer IC chip 2which is, for example, 4 to 6 inches by ultrasonic bump bonding usingfine Au bonding lines each having a diameter of, for example,approximately 25 to 35 μm.

During the flip chip bonding process (FCB process), as shown in theprocess diagram of the flip-chip bonding process in FIG. 5, the wafer ICchip 2 is picked up by a nozzle such as an inverted pyramidal collet orthe like, is turned over, and is passed on to an nozzle tip of anultrasonic horn. Then, the IC chip 2 is aligned and is chip-mounted on amounting area of the base 1 with high precision by a system such as animage recognition system provided in the flip chip bonding apparatus.

Since the pad 14 provided with the bump 4 is, as in above, loadedseveral times with weight and ultrasonic waves, it is possible that thepad 14 suffers from damage. However, this embodiment prevents suchdamage in a manner described below.

In this embodiment, the vibration direction US2 of the ultrasonic wavesfor ultrasonic bonding and for forming bumps on the IC chip 2 shown inFIG. 15, and vibration direction US1 of the ultrasonic waves forperforming a ultrasonic bonding of the IC chip 2 and the base 1 shown inFIG. 14 are set to be different, preferably, in directions which differfrom one another by 90 degrees.

By setting the vibration direction US1 and the vibration direction US2differently, damage to the pad 14 due to repetitively applying a load byultrasonic waves can be prevented.

The present invention is not limited to the above-described embodiments,and various modifications are possible without departing from the scopeof the claims.

For example, although the description has been made with regard to aquartz crystal oscillator in which a single-chip-type semiconductorintegrated circuit having an oscillating circuit is used and in which anAT-cut quartz crystal resonator element is used as a piezoelectricresonator element, the present invention is not limited to this. Forexample, the present invention can be applied to any piezoelectricdevice having a semiconductor integrated circuit such as avoltage-controlled oscillator (VCXO), a temperature-compensatedoscillator (TCXO), a SAW oscillator, real time clock modules.Furthermore, the present invention is also applicable to a piezoelectricdevice in which a quartz crystal resonator chip or a SAW chip is mountedin a package by flip-chip bonding.

As described above, according to the present invention, because of thestructure in which an opening is formed in the center of the baseprovided with an input/output electrode pattern, a semiconductorintegrated circuit is mounted in the center of the opening, and thesemiconductor integrated circuit is connected by a plurality of bumps tothe electrode pattern on the base, the stress is evenly distributed overthe semiconductor integrated circuit and stress concentration at aspecific bump can be eliminated. Accordingly, a piezoelectric oscillatorof superior configuration which is free of jointing failure between thebump and the electrode pattern can be provided.

According to the present invention, because of the structure in whichdummy bumps are formed on the active element surface of thesemiconductor integrated circuit, and the dummy bumps of thesemiconductor integrated circuit are connected to the electrode patternon the base, the stress applied to the bumps can be evenly distributed.Also, a bonding process using ultrasonic waves can be carried out in awell-balanced manner, the semiconductor integrated circuit is preventedfrom being mounted in an angled manner, and a piezoelectric oscillatorof high quality can be provided.

Furthermore, according to the present invention, by filling an underfillmaterial around the semiconductor integrated circuit so as to cover theentire semiconductor integrated circuit, i.e., including the rearsurface of the semiconductor integrated circuit, is not only thereliability of bonding between the semiconductor integrated circuit andthe base enhanced, but also heat from the semiconductor integratedcircuit can be conducted through the underfill material and can beradiated to the outside of the package.

According to the present invention, by regulating the vibrationdirection of ultrasonic waves applied to the semiconductor integratedcircuit, short-circuits between adjacent bumps can be prevented,ultrasonic bonding can be carried out securely, i.e., bonding betweenevery bump and electrode pattern can be performed in an even manner, anda high quality piezoelectric oscillator with a superior yield can beprovided.

According to the present invention, by shaping each of a plurality ofbumps on the semiconductor integrated circuit to have two levels, forexample, one formed to be 80 to 90 μm in diameter and 30 to 35 μm inheight, and the other formed to be 40 to 45 μm in diameter and 30 to 35μm in height, the gap between the semiconductor integrated circuit andthe base can be maintained to be several tens of μm (approximately 30μm), thereby performing ultrasonic bonding in a stable manner, i.e.,without experiencing short circuits, bonding shear, or the like.

According to the present invention, because a protrusion is formed in atleast one side wall of the base opposing a side of the semiconductorintegrated circuit, the underfill material applied through an applicatorsuch as a dispenser can completely fill the gap which is a region of thesemiconductor integrated circuit around the bumps, and the bump portioncan be securely coated with the underfill material. Also, by thisstructure, it becomes possible to apply a little underfill material,thereby preventing the underfill material from contacting to an AT-cutquartz crystal resonator, etc., and avoiding inconveniences such asoscillation termination, and variation in oscillation frequency.

According to the present invention, by setting the vibration directionof ultrasonic waves for ultrasonic bonding and for forming the bumps onthe semiconductor integrated circuit and the vibration direction ofultrasonic waves for performing ultrasonic bonding of the semiconductorintegrated circuit and a package differently, damage due to repetitivelyapplying a load by the ultrasonic waves can be prevented.

INDUSTRIAL APPLICABILITY

As described above, the present invention is suitable when used as apiezoelectric device having a package including a semiconductorintegrated circuit and a piezoelectric resonator element and as a methodfor manufacturing the same.

What is claimed is:
 1. A piezoelectric device, comprising: asemiconductor integrated circuit; and a piezoelectric resonator element,the semiconductor integrated circuit and the piezoelectric resonatorelement being included in a package, a plurality of bumps being formedat two opposing sides of an active element surface of the semiconductorintegrated circuit, the semiconductor integrated circuit being mountedin a center of an opening formed in a center of a base, and thesemiconductor integrated circuit being connected to an input/outputelectrode pattern through the plurality of bumps by ultrasonic bonding,each of the plurality of bumps formed on the semiconductor integratedcircuit being shaped to have two levels, a first level having a diameter0.8 to 0.9 times and a second level having a diameter 0.4 to 0.45 timesthe length of an opening in a pad provided on the active element surfaceof the semiconductor integrated circuit.
 2. The piezoelectric deviceaccording to claim 1, wherein the base includes a layered part, whichsurrounds the semiconductor integrated circuit, for mounting thepiezoelectric resonator element, the layered part comprising at leasttwo layers, including a first layer and a second layer, the first layerbeing below the second layer, wherein an opening of the first layer isformed to he larger than an opening of the second layer.
 3. Thepiezoelectric device according to claim 1, the plurality of bumps formedon the semiconductor integrated circuit being formed at regularintervals on a center portion of an active element surface of thesemiconductor integrated circuit.
 4. The piezoelectric device accordingto claim 1, the plurality of bumps formed on the semiconductorintegrated circuit being concentrically formed about a center of anactive element surface of the semiconductor integrated circuit.
 5. Thepiezoelectric device according to claim 1, further comprising a dummybump formed on an active element surface of the semiconductor integratedcircuit.
 6. The piezoelectric device according to claim 5, the dummybump formed on the semiconductor integrated circuit being connected tothe electrode pattern on the base.
 7. The piezoelectric device accordingto claim 1, a protrusion being formed in at least one side wall of thebase facing the side of the semiconductor integrated circuit andprotruding into the opening to form the protrusion.
 8. The piezoelectricdevice according to claim 7, the protrusion being formed in each of sidewalls of the base facing two sides along the longitudinal direction ofthe semiconductor integrated circuit.
 9. The piezoelectric deviceaccording to claim 7, the protrusion formed in the side wall of the basehaving a substantially same height as, or is higher than, thesemiconductor integrated circuit.
 10. The piezoelectric device accordingto claim 7, wherein a gap between the protrusion formed in the side wallof the base and the semiconductor integrated circuit being set to arange between 0.05 and 0.15 mm.
 11. The piezoelectric device accordingto claim 1, a vibration direction of ultrasonic waves applied to thesemiconductor integrated circuit being perpendicular to two opposingsides of the active element surface of the semiconductor integratedcircuit at which the plurality of bumps are formed.
 12. Thepiezoelectric device according to claim 1, a printing direction of theelectrode pattern on the base being the same as a vibration direction ofultrasonic waves applied to the semiconductor integrated circuit. 13.The piezoelectric device according to claim 1, wherein the first levelis 80 to 90 μm in diameter and 30 to 35 μm in height, and the secondlevel is 40 to 45 μm in diameter and 30 to 35 μm in height.
 14. Thepiezoelectric device according to claim 1, the base comprising a ceramiccomposite substrate.
 15. The piezoelectric device according to claim 1,the plurality of bumps formed on the semiconductor integrated circuitbeing Au bumps.
 16. The piezoelectric device according to claim 1, alongitudinal direction of the electrode pattern on the base being thesame as a vibration direction of ultrasonic waves applied to thesemiconductor integrated circuit.
 17. The piezoelectric device accordingto claim 1, a vibration direction of ultrasonic waves for ultrasonicbonding and for forming bumps on the semiconductor integrated circuitbeing different from a vibration direction of ultrasonic waves forperforming ultrasonic bonding of the semiconductor integrated circuit tothe package.
 18. The piezoelectric device according to claim 7, whereina gap is defined between the protrusion and the semiconductor integratedcircuit in that the protrusion does not contact the semiconductorintegrated circuit.
 19. The piezoelectric device according to claim 18,wherein an underfill material permeates the gap and fills a portion ofthe integrated circuit having the plurality of bumps.
 20. Thepiezoelectric device according to claim 1, wherein an underfill materialpermeates to the first layer and fills a portion of the integratedcircuit having the plurality of bumps.